A radio receiver may be used to recover a “baseband” signal (e.g., a radio signal having a first frequency) from transmitted data (e.g., typically having a second frequency different from, and oftentimes higher than, the first frequency). For example, a transmitted signal may have an AM sinusoidal waveform (e.g., generally having the form A(t)cos(ωct), where A(t) can be any time-varying signal representing the transmitted data; and cos(ωct) is the baseband signal, where ω=2πf, and “f” is the frequency of the sinusoidal waveform, and “t” represents time). In some cases, the baseband signal may include frequencies near 0 Hz (e.g., 1 Hz). In some wireless communication signal systems, transmitted signals can include original low frequency radio signal portions that are modulated to the higher transmitted carrier frequencies (e.g., in a radio-frequency [RF] signal) for transmission. Such original low frequency components (i.e., the baseband radio signal) can then be converted or recovered from the relatively high frequency components by using a radio receiver.
In a typical conversion to baseband signal frequencies, one or two mixers or multiplier circuits can be used for a “direct down” conversion approach where incoming data (e.g., a radio signal) is directly converted from the transmission frequency or broadcast channel (e.g., typically from about 40 to about 60 kHz) to the baseband frequency (e.g., about 1 Hz) in a receiver. However, one drawback of this approach is a potential mismatch between the transmission frequency and a reference frequency of the receiver. If those frequencies are not identical, a “delta” frequency or frequency difference will be converted into a signal portion or component in a receiver output waveform for the recovered radio signal.
Several different architectures have been used to solve the problem of mismatch between the transmission frequency and the reference frequency of the receiver. One such architecture, shown in FIG. 1, employs delay-locked loop 120 in a receiver indicated by the general reference character 100. The delay element 108 is used to take a signal from a reference source, in this instance the voltage-controlled oscillator 110 coupled to a phase-locked loop 112 that receives a reference clock signal from the reference clock generator 114, and provide a delayed (or phase-shifted) signal as a reference oscillator with the delay being variable corresponding to its gain and the value applied to its control input. The output from the delay element (or reference oscillator) is used in the I-channel in processing the transmitted radio signal to obtain a recovered radio signal (transmitted data).
The signal from reference oscillator is also used in a feedback loop to set the level of control signal, x, for the delay element. The signal is phase shifted in a 90° phase shifter 106. The resulting signal is combined with the radio signal in the Q-channel mixer. The output of the Q-channel mixer is then processed by a low pass filter 104-Q and the resulting signal is used as the control signal for the delay element.
From an analysis of the circuit, it is observed that the controlling input to the delay element is negatively proportional to the delta of time. This implies that after a long period of time, the control voltage of the delay element would also become increasingly large in magnitude. This may not be practical for a system with limited control or power supply voltage. To overcome this issue, two potential solutions have been identified.
One method involves repeatedly resetting the DLL at a fixed rate. FIG. 2 illustrates a reset circuit for resetting a DLL 200 at a fixed rate. In the DLL 200, mixer 202 (which corresponds to mixer 102-Q in FIG. 1) provides an output to low-pass filter 210 (which corresponds to filter 104-Q in FIG. 1) formed by resistor R1, capacitor C1, and operational amplifier 204 (which receives both the RC-filtered output of mixer 202 and a reference voltage). A delay control signal output (x) from low-pass filter 210 is input into delay line 206 (which corresponds to delay line 108 in FIG. 1), which also receives a reference clock via reference path 208. Switch S1 resets the low-pass filter by discharging capacitor C1. During a reset operation, switch S1 is closed (e.g., in response to an active reset signal) for a length of time sufficient to discharge substantially all of the charge on capacitor C1. To reset the DLL at a fixed rate, the reset switch is periodically pulsed.
At large phase errors, the control voltage should return to its correct delay value after being reset. This will take a certain amount of time, depending upon the loop response time. During this reset time, the loop will generally be in error and may cause the output of the I-channel to decrease in value. With a large enough signal bandwidth-to-reset period ratio, this can be filtered out with a low pass filter. However, if the bandwidth of the data is near the reset frequency, a ripple in the output may occur. This ripple can become significant enough to cause errors, especially in the presence of noise.
The second method entails two replica delay lines of the same length of the main delay line that provide a 0 and 2π reference control voltage. The control voltage of the main delay line is then reset when it reaches either reference value.
Referring to FIGS. 3A and 3B, this method employs a DLL reset circuit having replica circuit portions, utilizing sine/cosine function repeatability. The DLL reset circuit is indicated by the general reference character 300. As shown in FIG. 3A, replica circuit portions, such as delay lines 304 and 306, are used in detecting the 2π threshold. The outputs of replica delay lines 308 can be monitored until the output of delay line 304 (controlled by xa) equals cos(0) and the output of delay line 306 (controlled by xb) equals cos(2π). Thus, xa and xb may have fixed or predetermined values such that xa is substantially equal to a predetermined minimum value for x, and xb is substantially equal to a predetermined maximum value for x. Referring now to FIG. 3B, comparator circuit 312 can then be used to detect when delay control signal x gets as large as xb so that a pulse can be provided to close switch S1 in low-pass filter 310 (which corresponds to filter 104-Q in FIG. 1) formed by resistor R1, capacitor C1, and operational amplifier 314. When S1 is closed, operational amplifier 314 can produce a unity gain feedback for input xa such that delay control signal x can be reset to the value of input xa. Of course, the xa and xb inputs may be switched in the scheme of FIG. 3B for a negative-ramping x.
This second method consumes extra power (e.g., by the delay lines 304, 306) to provide the reference control voltage. Also, the output of delay lines 304, 306 can vary significantly as a function of process parameters. This means that the reference voltages may have to move significantly to compensate for this source of error.